Min-Mozhi — a modern, safe-by-default HDL with compiler + simulator, built in Rust

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Min-Mozhi is a hardware description language that compiles to synthesizable Verilog and ships with its own event-driven simulator. It’s designed for teaching digital design and for anyone who wants a safer, more ergonomic alternative to writing raw Verilog.

module Counter(WIDTH: int = 8) {
  clock clk
  reset rst
  out count: bits[WIDTH]
  reg value: bits[WIDTH] = 0
  on rise(clk) { value <- value +% 1 }
  count = value
}

What’s under the hood:

  • Compiler (Rust): lexer → parser → AST → type/safety checker → Verilog emitter — ~21 modules, 476 passing tests
  • Simulator: event-driven, VCD output, bit-matched against Icarus Verilog
  • Safety by default: no inferred latches, silent truncation, multiple drivers, or uninitialized regs — all compile-time errors with stable error codes
  • CLI: mimz check/compile/sim/test/lsp with --json, --watch, VS Code extension
  • Status: v0.1.0 pre-release — compiler + simulator complete, native synthesis (Yosys/nextpnr) on the roadmap

It’s new and experimental (educational project, honestly framed), but nothing built here is a dead end — it always emits standard Verilog.

Repo: github.com/Naveen2070/min-mozhi — MIT/Apache-2.0.

Would love feedback, PRs, or issues — especially from folks working with HDLs, FPGAs, or Rust compilers.