Proposed Theme for FOSS Hack 2026
Netlist-to-Verilog Converter for Digital Circuits in eSim
Participants will develop a tool that converts digital netlists generated in eSim into synthesizable Verilog code. This will enable digital circuits designed using the schematic editor to be exported and used in RTL-based design flows.
The script should parse the digital netlist and map commonly used components such as AND, OR, NOT, XOR gates, multiplexers, and flip-flops into equivalent Verilog constructs.
Expected Outputs:
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A script/tool that parses eSim digital netlists
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Mapping of supported digital components to synthesizable Verilog
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Generated Verilog module for the given circuit
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Example test circuits demonstrating correct conversion
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Documentation explaining usage and supported components
Participants are encouraged to use open-source tools and contribute improvements that can be integrated into the eSim ecosystem.
This track aims to strengthen the digital design capabilities of eSim and enable interoperability with modern open-source digital design workflows.